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EVALUATION KIT AVAILABLE
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TC520A
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY
FEATURES
s s s s s s Converts TC500/500A/510/514 to Serial Operation Programmable Conversion Rate and Resolution for Maximum Flexibility Supports up to 17 Bits of Accuracy Plus Polarity Bit Low Power Operation: Typically 7.5mW 14-Pin DIP or 16-Pin SOIC Packages Polled or Interrupt Mode Operation
GENERAL DESCRIPTION
The TC520A Serial Interface Adapter provides logic control for TelCom's TC500/500A/510/514 family of dual slope, integrating A/D converters. It directly manages TC500 converter phase control signals A, B, and CMPTR thereby reducing host processor task loading and software complexity. Communication with the TC520A is accomplished over a 3 wire serial port. Key converter operating parameters are programmable for complete user flexibility. Data conversion initiated when the CE input is brought low. The converted data (plus overrange and polarity bits) are held in an 18 bit shift register until read by the processor, or until the next conversion is completed. Data may be clocked out of the TC520A at any time, and at any rate the user prefers. A Data Valid (DV) output is driven active at the start of each conversion cycle indicating the 18 bit shift register update has just been completed. This signal may be polled by the processor, or can be used as data ready interrupt. The TC520A timebase can be derived from an external frequency source of up to 6MHz; or can operate from its own external crystal. It requires a single 5V logic supply and dissipates less than 7.5mW.
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ORDERING INFORMATION
Part No. TC520ACOE TC520ACPD TC500EV Package Operating Temp. Range
16-Pin SOIC (Wide) 0C to +70C 14-Pin Plastic DIP 0C to +70C Evaluation Kit for TC500 Family
PIN CONFIGURATION
VDD VDD DGND CMPTR B A OSCOUT OSCIN 1 2 3 4 5 6 7 8 TC520ACOE 16 15 14 13 12 11 10 9 CE DV LOAD DIN DCLK DOUT READ N/C
1 2 3 4 5 6 7
TC520ACPD
14
CE
DGND CMPTR B A OSCOUT OSCIN N/C
13 DV 12 LOAD 11 DIN 10 DCLK 9 8
DOUT READ
FUNCTIONAL BLOCK DIAGRAM
VDD GND 1 2
Pin Out of 14-Pin Package
11 8-BIT SHIFT REG. 8 GATE 8-BIT COUNTER /256 GATE DIN
A B CMPTR CE DV
5 4 3 14 13 LOGIC CONTROL
TIME OUT FORCE AUTO-ZERO POLARITY BIT 9 18-BIT SHIFT REGISTER CLEAR COUNT 16 GATE 10 DOUT DCLK 12 LOAD
OSCIN OSCOUT
7 6 /4 SYSCLK GATE 16-BIT COUNTER OVERRANGE BIT 8 READ
TC520A-1 9/16/96
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TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage (VDD) ........................................ +6.0V Input Voltage, All Inputs (VIN) ............ - 0.3V to VDD +0.3V Operating Temperature Range (TA) ............. 0C to +70C Storage Temperature Range (TSTG) ..... - 65C to +150C Lead Temperature (Soldering, 10 sec) (TSDR) ...... +300C
* Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the Operational Specifications is not implied. Any exposure to Absolute Maximum Rating Conditions may affect device reliability.
ELECTRICAL CHARACTERISTICS: VDD = 5V, fosc = 1 MHz, TA = +25C, unless otherwise specified.
Symbol
Supply VDD IDD Input Characteristics VIL VIH IIL IPD IPU
Parameter
Operating Voltage Range Supply Current Low Input Voltage High Input Voltage Input Leakage Current Pull-down Current (CE) Pull-up Current (READ, LOAD)
Min
4.5 -- -- 2.0 -- -- -- -- 3.5 -- -- -- 250 1 450 1 50 150 150 250 250 -- --
Typ
5 0.8 -- -- -- 5 5 0.2 4.3 -- 1.0 -- -- -- -- -- -- -- -- -- -- 0.5 100
Max
5.5 1.5 0.8 -- 10 -- -- 0.3 -- 250 4.0 6.0 -- -- -- -- -- -- -- -- -- -- --
Unit
V mA V V A A A V V nsec MHz MHz nsec sec nsec sec nsec nsec nsec nsec nsec msec msec
Output Characteristics (IOUT = 250 A, VDD = 5V) VOL Low Output Voltage VOH High Output Voltage tR, tF CL = 10pF, Rise/Fall Times Oscillator (OSCIN, OSCOUT) fXTL fOSC Timing Characteristics tRD tRS tDRS tLS tDLS tPWL tPWH tLDL tLDS Parameter tIZ tAZI Crystal Frequency External Frequency (OSCIN) READ Delay Time Data Read Setup Time DCLK to DOUT Delay LOAD Setup Time Data Load Setup Time DCLK Pulse Width Low Time DCLK Pulse Width High Time Load Default Low Time Load Default Setup Time Integrator ZERO Time Autozero (RESET) Time at Power-Up
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TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
DETAILED DESCRIPTION
The TC520A input and output signals are outlined in the table below.
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2 3 4 5 6 7
PIN DESCRIPTIONS
Pin No. Pin No. 14-Pin PDIP 16-Pin SOIC Package Package
1 2 3 1 2 3
Symbol
VDD DGND CMPTR
Description
Input. +5V 10% power supply input with respect to DGND. Input. Digital Ground. Input, active high or low (depending on polarity of the voltage input to A/D converter). This pin connects directly to the zero-crossing comparator output (CMPTR) of the TC5xx A/D converter. A High-to-Low state change on this pin causes the TC520A to terminate the de-integrate phase of conversion. Output, active high. The A and B outputs of the TC520A connect directly to the A and B inputs of the TC5xx A/D converter connected to the TC520A. The binary code on A, B determines the conversion phase of the TC5xx A/D converter: (A, B) = 01 places the TC5xx A/D converter into the Auto Zero phase; (A, B) =10 for Integrate phase (INT); (A, B) =11 for De-integrate phase (DINT) and (A, B) = 00 for Integrator Zero phase (IZ). Please see the TC500 family data sheets for a complete description of these phases of operation. Output, active high. See pin 4 description above. Input. This pin connects to one side of an AT-cut crystal having a effective series resistance of 100 (typ) and a parallel capacitance of 20pF (typ). If an external frequency source is used to clock the TC520A, this pin must be left floating. Input. This pin connects to the other side of the crystal described in pin 6 above. The TC520A may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse train having a duty cycle of 30% (minimum); rise and fall times of 15nsec and a min/ max amplitude of 0 to VIH. If an external frequency source is used, pin 6 must be left floating. A maximum operating frequency of 4MHz (crystal) or 6MHz (external clock source) is permitted. No connection on 16 pin package version. No connection on 16 pin package version. Input, active low, level and negative edge triggered. A high-to low transition on READ loads serial port output shift register with the most recent converted data. Data is loaded such that the first bit transmitted from the TC520A to the processor is the overrange bit (OVR), followed by the polarity bit (POL) (high = input positive; low = input negative). This is followed by a 16 bit data word (MSB first). (OVR is available at the DOUT as soon as READ is brought low. This bit may be used as the 17th data bit if so desired.) The DOUT pin of the serial port is enabled only when READ is held low. Otherwise, DOUT remains in a high impedance state. A serial port read access cycle is terminated at any time by bringing READ high. Output, logic level. Serial port output pin. This pin is enabled only when READ is low (see READ pin description). Input, positive and negative edge triggered. Serial port clock. With READ low, serial data is clocked into the TC520A at each low-to-high transition of DCLK, and clocked out of the TC520A on each high-to-low transition of DCLK. A maximum serial port DCLK frequency of 3MHz is permitted.
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4
4
B
5 6
5 6
A OSCOUT
7
7
OSCIN
8
8 9 10
N/C N/C READ
9 10
11 12
DOUT DCLK
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TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
PIN DESCRIPTIONS (Cont.)
Pin No. Pin No. 14-Pin PDIP 16-Pin SOIC Package Package
11 13
Symbol
DIN
Description
Input, logic level. Serial port input pin. The TC5xx A/D converter integration time (TINT) and Autozero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. Input, active low; level and edge triggered. The LOAD VALUE is clocked into the 8 bit shift register on board the TC520A while LOAD is held low. The LOAD VALUE is then transferred into the TC520A internal timebase counter (and becomes effective) when LOAD is returned high. If so desired, LOAD can be momentarily pulsed low (eliminating the need to clock a LOAD VALUE into DIN). In this case, the current state of DIN is clocked into the TC520A timebase counter selecting either a count of 65536 (DIN = High), or count of 32768 (DIN = Low). Output, active low. DV is brought any time the TC520A is in the AZ phase of conversion. This occurs when either the TC520A initiates a normal AZ phase by setting A, B, equal to 01; or when CE is pulled high (which overrides the normal A, B sequencing and forces an AZ state). DV is returned high when the TC520A exits AZ. Input, active low, level triggered. Conversion will be continuously performed as long as CE remains low. Pulling CE high causes the conversion process to be halted, and forces the TC520 into the AZ mode for as long as CE remains high. CE should be taken high whenever it is necessary to momentarily suspend conversion (for example: to change the address lines of an input multiplexer). CE should be pulled high only when the TC520A enters an AZ phase (i.e. when DV is low). This is necessary to avoid excessively long integrator discharge times which could result in erroneous conversion. This pin should be grounded if unused. It should be left floating if a 0.01F RESET capacitor is connected to it (see Applications section).
12
14
LOAD
13
15
DV
14
16
CE
DETAILED DESCRIPTION (CONT.)
TC520A Timing The TC520A consists of a serial port and state machine. The state machine provides control timing to both the TC5xx A/D converter connected to the TC520A, as well as sequential timing for TC520A internal operation. All timing is derived from the frequency source at OSCIN and OSCout. This frequency source can be either an externally-provided clock signal, or external crystal. If an external clock is used, it must be connected to the OSCIN pin and OSCOUT must remain floating. If a crystal is used, it must be connected between the OSCIN and OSCOUT and physically located as close to the OSCIN and OSCOUT pins as possible. The incoming frequency is internally divided by 4 and the resulting clock (SYSCLK) controls all timing functions. TC5xx A/D Converter Control Signals The TC520A control outputs (A, B) and control input (CMPTR) connect directly to the corresponding pins of the TC5xx A/D converter. A conversion is consummated when
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A, B have been sequenced through the required 4 phases of conversion: Auto Zero (AZ), Integrate (INT), De-integrate (DINT) and Integrator Zero (IZ) (See Figure 1). The Auto Zero phase compensates for offset errors in the TC5xx A/D converter. The integrate phase connects the voltage to be converted to the TC5xx A/D converter input (resulting in an integrator output dv/dt directly proportional to the magnitude of the applied input voltage). Actual A/D conversion (counting) is initiated at the start of the DINT phase and terminates when the integrator output crosses 0V. The integrator output is then forced to 0V during the IZ phase and the converter is ready for another cycle. Please see the TC500/500A/510/ 514 data sheet for a complete description of these phases. The number of SYSCLK periods (counts) for the AZ and INT phases is determined by the LOAD VALUE. The LOAD VALUE is a single byte that must be loaded into the most significant byte of 16 bit counter on-board the TC520A during initialization. The lower byte of this counter is pre-loaded to a value of 0FFH (25610) and cannot be changed. The LOAD VALUE (upper 8 bits of the counter) can be programmed over a range of 0FFH to 00H (corresponding to TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
a range of AZ = INT = 256 counts to 65536 counts). (See Figure 2). The LOAD VALUE sets the number of counts for both the AZ and INT phases and directly affects resolution and speed of conversion. The greater the number of counts allowed for AZ and INT; the greater the A/D resolution, but the slower the conversion speed. The time period required for the DINT phase is a function of the amount of voltage stored on the integrator during the INT phase, and the value of VREF. The DINT phase is initiated by the TC520A immediately after the INT phase, and terminated when the TC5xx A/D converter changes the state of the CMPTR input of the TC520A (indicating a zero crossing). In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN (max)/2). Choosing these values guarantees a full count (maximum resolution) during DINT when VIN = VIN(max). The IZ phase is initiated immediately following the DINT phase maintained until the CMPTR input transitions high. This indicates the integrator is initialized and ready for another conversion cycle. This phase typically takes 2msec. Serial Port Control Signals Communication to and from the TC520A is accomplished over a 3 wire serial port. Data is clocked into DIN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK. READ must be low to read from the serial port and can be taken high at any time, which terminates the read cycle, and releases DOUT to a high impedance state. Conversion data is shifted to the processor from DOUT in the following order: Overrange bit (which can also be used as the 17th data bit), Polarity bit, conversion data (MSB first). TC520A Initialization Initialization of the TC520A consists of: (1) Power-On RESET of the TC500/520A (forcing the TC520A into an AZ phase). (2) Initializing the TC520A LOAD VALUE. Power-On RESET The TC520A powers-up with A, B = 00 (IZ Phase), awaiting a high logic state on CMPTR, which must be initiated by forcing the TC520A into the AZ phase. This can be accomplished in one of two ways: (1) External hardware (processor or logic) can momentarily taking LOAD or CE low for a minimum of 100 msec (tAZI); or (2) A .01F RESET capacitor can be connected from CE to VCC to generate a power-on pulse on CE. Load Value Initialization The LOAD VALUE is the preset value (high byte of the SYSCLK timing counter) which determines the number of counts allocated to the AZ and INT phases of conversion. This value can be calculated using the TC520A spreadsheet within the TC500 Design Spreadsheet software, or can be setup as shown in the following example: (1) Select VREF, TDINT Choose the TC5xx A/D converter reference voltage (VREF) to be half of the maximum A/D converter input voltage. For example, if VIN max = 2.5V; choose VREF = 1.75V. This forces the maximum deintegration time (TDINT) to be equal to twice the maximum integration time (TINT) ensuring a full count (maximum resolution) during DINT. (2) Calculate TINT The TC520A counter length is 16 bits (65536). Allowing the full 65536 counts for TDINT results in a maximum TINT = 65536/2 or 32768. (3) Select SYSCLK Frequency SYSCLK frequency directly affects conversion time. The faster the SYSCLK, the faster the conversion time. The upper limit SYSCLK frequency is determined by the worst case delay of the TC500 comparator (which for the TC500 and TC500A is 3.2sec). While a faster value for SYSCLK can be used, operation is optimized (error minimized) by choosing a SYSCLK period (1/SYSCLK frequency) that is greater than 3.2sec. Choosing TSYSCLK =
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APPLICATIONS
TC500 Series A/D Converter Component Selection The TC500/500A/510/514 data sheet details the equations necessary to calculate values for integration resistor (RINT) and capacitor (CINT); auto zero and reference capacitors CREF and CAZ and voltage reference VREF. All equations apply when using the TC520A, except integration time (TINT) and Autozero time (TAZ) are functions of the SYSCLK period (timebase frequency and LOAD VALUE). TelCom offers a ready-to-use TC5xx A/D converter design tool on a 3 1/2 inch diskette (Windows format). The TC500 Design Spreadsheet is an Excel-based spreadsheet that calculates values for all components as well as the TC520A LOAD VALUE. It also calculates overall converter performance such as noise rejection, converter speed, etc. This software is included in the TC500EV hardware evaluation kit and is also available free of charge from your local TelCom representative.
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TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
4sec makes the SYSCLK frequency equal to 250kHz. This makes the external crystal (or frequency source) equal to 1.0MHz (since SYSCLK = crystal frequency/4). Calculating integration time (in msec) using TSYSCLK = 4sec, TINT = sec x 32768 = 131msec. (4) Calculate Load Value Plug the TINT and TSYSCLK values into the equation and convert the resulting value to hexadecimal: LOAD VALUE = [(65536 - (TINT/TSYSCLK)] 256 In this example, LOAD VALUE = 128(10) = 10H. Therefore, a LOAD VALUE of 10H is loaded to the TC520A. If the desired TINT was 100msec instead of 131msec, the LOAD VALUE would be 9EH, and so on. The TC520A LOAD VALUE must be initialized on power-up, and can be reinitialized as often as desired thereafter. This is accomplished by bringing the LOAD input low while transmitting the appropriate LOAD VALUE to the TC520A as shown in Figure 1 and Figure 2. Polled vs. Interrupt Operation The TC520A can be accessed at any time by the host microprocessor. This makes operation in a polled environment especially easy since the most recently converted data is available to the processor as needed. The TC520A can also be used in an interrupt environment by connecting DV to the IRQ line of the processor. Since AZ is the first phase of a new conversion cycle, the most recently converted data will be available as soon as DV goes low. If so desired, the interrupt service routine can also modify the LOAD VALUE during the DV = low interval. Opto-Isolated Applications The 3 wire serial port of the TC520A can be optoisolated for applications requiring isolated data acquisition. The additional control lines (LOAD, DV, READ) are normally not needed in such applications, but can also be brought across the isolation barrier with the addition of a second isolator.
TC520A CONVERSION STATE AZ LOAD INT DINT IZ AZ INT DINT IZ AZ AZ INT
CE is pulled high only when during AZ (DV = LOW)
CE
LOAD VALUE updated and conversion started DIN, DCLK LOAD VALUE shifted into DIN
New LOAD VALUE can be loaded (if so desired) LOAD VALUE
DV
TC520A held in AZ phase as long as CE = HIGH
Figure 1. TC520A Initialization and Start/Stop Conversion Timing Relationships
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TELCOM SEMICONDUCTOR, INC.
SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
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TC520A CONVERSION STATE AZ LOAD INT DINT IZ AZ INT DINT IZ AZ INT
2 3 4
CE
LOAD VALUE updated and conversion started
DIN, DCLK
LOAD VALUE shift into DIN
DV
Figure 2. Load Value Modify Cycle
+5V
CINT 10k 100k
VIN+
1 INT CAZ 4 BUF 11 IN+ 10 IN- 9 REF+ 3
V+ 16 CRYSTAL 14 CMPTR 13 B 12 A TC500 6 CR- CR+ 7 CREF
6
5
OSCOUT OSCIN CMPTR B A DV CE 1 V+ 12 LOAD 8 READ 10 DCLK DIN 11 DOUT 9
LD RD SK SO SI
CAZ RINT .01
VIN-
7 3 4 5 13 14
6 7
.01 100k TC05 ANALOG GROUND
8 REF- 5 COM
15 GND V2 -5V
2 GND TC520A
CE
DGND
DV
Figure 3. Typical System Application
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TELCOM SEMICONDUCTOR, INC.
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SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY TC520A
READ TIMING READ tRD DOUT tDRS DCLK tPWL DIN DCLK tRS LOAD
LOAD TIMING
LOAD DEFAULT TIMING LOAD tLDL tPWH DIN tLDS
tLS tDLS
READ READ FORMAT DOUT DCLK OVR POL MSB LSB
LOAD LOAD FORMAT DIN DCLK MSB LSB
Figure 4. TC520A Timing Diagram
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TELCOM SEMICONDUCTOR, INC.

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